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» A Low Power Highly Associative Cache for Embedded Systems
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CLUSTER
2008
IEEE
15 years 4 months ago
High message rate, NIC-based atomics: Design and performance considerations
—Remote atomic memory operations are critical for achieving high-performance synchronization in tightly-coupled systems. Previous approaches to implementing atomic memory operati...
Keith D. Underwood, Michael Levenhagen, K. Scott H...
INFOCOM
1999
IEEE
15 years 1 months ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. ...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da...
CBSE
2004
Springer
15 years 3 months ago
Introducing a Component Technology for Safety Critical Embedded Real-Time Systems
Safety critical embedded real-time systems represent a class of systems that has attracted relatively little attention in research addressing component based software engineering. ...
Kristian Sandström, Johan Fredriksson, Mikael...
IPPS
2010
IEEE
14 years 7 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
LCTRTS
2007
Springer
15 years 3 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...