19 search results - page 3 / 4 » A Mask Reuse Methodology for Reducing System-on-a-Chip Cost |
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
DATE
2008
IEEE
14 years 22 days ago
2008
IEEE
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
OOPSLA
2005
Springer
13 years 11 months ago
2005
Springer
Frameworks and libraries change their APIs during evolution. Migrating an application to the new API is tedious and disrupts the development process. Although some tools and techn...
IPPS
2007
IEEE
14 years 17 days ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...