383 search results - page 1 / 77 » A Methodology for High Level Power Estimation and Exploratio... |
84
Voted
GLVLSI
1998
IEEE
15 years 5 months ago
1998
IEEE
ASPDAC
2007
ACM
15 years 5 months ago
2007
ACM
110
Voted
ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy...
122
Voted
DAC
1997
ACM
15 years 5 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
88
Voted
ICCD
2000
IEEE
15 years 10 months ago
2000
IEEE
el of abstraction by integrating a high-level estimation step. This results in a design loop which is tight led on high level of abstraction (called estimation loop in figure 1). ...