Sciweavers

485 search results - page 46 / 97
» A Model Checking Approach for Verifying COWS Specifications
Sort
View
RE
2001
Springer
15 years 2 months ago
Events and Constraints: A Graphical Editor for Capturing Logic Requirements of Programs
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
Margaret H. Smith, Gerard J. Holzmann, Kousha Etes...
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
15 years 3 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
APSEC
2009
IEEE
14 years 7 months ago
A Formal Framework to Integrate Timed Security Rules within a TEFSM-Based System Specification
Abstract--Formal methods are very useful in software industry and are becoming of paramount importance in practical engineering techniques. They involve the design and the modeling...
Wissam Mallouli, Amel Mammar, Ana R. Cavalli
ECOWS
2009
Springer
15 years 1 months ago
Run-time Verification of Behavioural Conformance for Conversational Web Services
— Web services exposing run-time behaviour that deviates from their behavioural specifications represent a major threat to the sustainability of a service-oriented ecosystem. It ...
Dimitris Dranidis, Ervin Ramollari, Dimitrios Kour...
DAC
1996
ACM
15 years 1 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson