Automatic test data generation leads to identify input values on which a selected point in a procedure is executed. This paper introduces a new method for this problem based on co...
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
In this paper, we introduce a Shared Multiple Rooted XORbased Decomposition Diagram XORDD to represent functions with multiple outputs. Based on the XORDD representation, we dev...
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
In a typical VLSI/PCB design, some modules are pre-placed in advance, and the other modules are requested to be placed without overlap with these pre-placed modules. The presence ...