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» A Network Congestion-Aware Memory Controller
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CF
2010
ACM
15 years 4 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
88
Voted
SSS
2010
Springer
158views Control Systems» more  SSS 2010»
14 years 10 months ago
Low Memory Distributed Protocols for 2-Coloring
In this paper we present new distributed protocols to color even rings and general bipartite graphs. Our motivation is to provide algorithmic explanation for human subject experime...
Amos Israeli, Mathew D. McCubbins, Ramamohan Patur...
CASES
2004
ACM
15 years 3 months ago
Translating affine nested-loop programs to process networks
New heterogeneous multiprocessor platforms are emerging that are typically composed of loosely coupled components that exchange data using programmable interconnections. The compon...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
NN
1998
Springer
14 years 11 months ago
Distributed ARTMAP: a neural network for fast distributed supervised learning
Distributed coding at the hidden layer of a multi-layer perceptron (MLP) endows the network with memory compression and noise tolerance capabilities. However, an MLP typically req...
Gail A. Carpenter, Boriana L. Milenova, Benjamin W...
CORR
2006
Springer
111views Education» more  CORR 2006»
14 years 11 months ago
An associative memory for the on-line recognition and prediction of temporal sequences
This paper presents the design of an associative memory with feedback that is capable of on-line temporal sequence learning. A framework for on-line sequence learning has been prop...
Joy Bose, Stephen B. Furber, Jonathan L. Shapiro