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» A Network on Chip Architecture and Design Methodology
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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 6 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
NOCS
2007
IEEE
15 years 6 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
MOBICOM
2006
ACM
15 years 5 months ago
A software architecture for physical layer wireless network emulation
Despite their widespread deployment, many aspects of wireless network performance are poorly understood, and there is great room from improvement in wireless network reliability a...
Glenn Judd, Peter Steenkiste
WWW
2006
ACM
16 years 15 days ago
The web structure of e-government - developing a methodology for quantitative evaluation
In this paper we describe preliminary work that examines whether statistical properties of the structure of websites can be an informative measure of their quality. We aim to deve...
Vaclav Petricek, Tobias Escher, Ingemar J. Cox, He...
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 6 days ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...