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» A Network on Chip Architecture and Design Methodology
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PARELEC
2006
IEEE
15 years 5 months ago
Application-Driven Development of Concurrent Packet Processing Platforms
We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we h...
Christian Sauer, Matthias Gries, Jörg-Christi...
ICRA
2003
IEEE
102views Robotics» more  ICRA 2003»
15 years 5 months ago
Two-dimensional signal transmission technology for robotics
The forms of communication available now are categorized into the one or three dimensional. One dimensional communication includes metal wires and optical fibers in which the elec...
Hiroyuki Shinoda, Naoya Asamura, Mitsuhiro Hakozak...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
15 years 6 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
TPDS
1998
122views more  TPDS 1998»
14 years 11 months ago
Managing Statistical Behavior of Large Data Sets in Shared-Nothing Architectures
—Increasingly larger data sets are being stored in networked architectures. Many of the available data structures are not easily amenable to parallel realizations. Hashing scheme...
Isidore Rigoutsos, Alex Delis
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
15 years 6 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu