522 search results - page 19 / 105 » A Note on Designing Logical Circuits Using SAT |
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
CSREAESA
2004
14 years 11 months ago
2004
To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flat-t...
FPL
2001
Springer
15 years 2 months ago
2001
Springer
Asynchronous logic design has been around for decades. However, only recently has it gained any commercial success. Research has focused on a wide variety of uses, from microproces...
ICCAD
1996
IEEE
15 years 2 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
MJ
2006
14 years 9 months ago
2006
This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulat...