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FPGA
2006
ACM
100views FPGA» more  FPGA 2006»
13 years 10 months ago
A generic lookup cache architecture for network processing applications
Abstract-- In this paper, we introduce a novel architecture for constructing caches for lookup operations that are used in a variety of network processing applications. The disting...
Janardhan Singaraju, John A. Chandy
ISCC
2005
IEEE
119views Communications» more  ISCC 2005»
13 years 12 months ago
A Systematic Approach to Building High Performance Software-Based CRC Generators
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
Michael E. Kounavis, Frank L. Berry
CASES
2008
ACM
13 years 8 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 9 days ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ASPLOS
2006
ACM
14 years 7 days ago
A performance counter architecture for computing accurate CPI components
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, J...