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FPGA
2009
ACM
343views FPGA» more  FPGA 2009»
15 years 8 months ago
Fpga-based face detection system using Haar classifiers
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kas...
ICS
2009
Tsinghua U.
15 years 8 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
CCGRID
2009
IEEE
15 years 8 months ago
C-Meter: A Framework for Performance Analysis of Computing Clouds
—Cloud computing has emerged as a new technology that provides large amount of computing and data storage capacity to its users with a promise of increased scalability, high avai...
Nezih Yigitbasi, Alexandru Iosup, Dick H. J. Epema...
RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
15 years 8 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
IEEEPACT
2009
IEEE
15 years 8 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...
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