1167 search results - page 182 / 234 » A Really Temporal Logic |
134
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DAC
1996
ACM
15 years 5 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
149
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APLAS
2007
ACM
2007
ACM
The Semantics of "Semantic Patches" in Coccinelle: Program Transformation for the Working Programmer
15 years 5 months ago
We rationally reconstruct the core of the Coccinelle system, used for automating and documenting collateral evolutions in Linux device drivers. A denotational semantics of the syst...
117
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ASPDAC
2007
ACM
15 years 5 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
116
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CMSB
2009
Springer
15 years 5 months ago
2009
Springer
Abstract. In systems biology, the number of models of cellular processes increases rapidly, but re-using models in different contexts or for different questions remains a challengi...
116
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ATVA
2006
Springer
15 years 5 months ago
2006
Springer
In the past decades, many formal frameworks (e.g. timed automata and temporal logics) and techniques (e.g. model checking and theorem proving) have been proposed to model a real-ti...