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» A Refactoring Approach to Parallelism
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141
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DATE
2007
IEEE
95views Hardware» more  DATE 2007»
15 years 10 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
121
Voted
DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 10 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ICSNC
2007
IEEE
15 years 10 months ago
Movement Prediction Using Bayesian Learning for Neural Networks
Nowadays, path prediction is being extensively examined for use in the context of mobile and wireless computing towards more efficient network resource management schemes. Path pr...
Sherif Akoush, Ahmed Sameh
ISORC
2007
IEEE
15 years 10 months ago
A Comparative Evaluation of EJB Implementation Methods
As E-businesses are becoming ubiquitous, enhancing the performance and scalability of ebusiness systems has become an increasingly important topic of investigation. As Vitruvius (...
Andreas Stylianou, Giovanna Ferrari, Paul D. Ezhil...
ISPASS
2007
IEEE
15 years 10 months ago
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad ...