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DATE
2009
IEEE
176views Hardware» more  DATE 2009»
15 years 4 months ago
Automated synthesis of streaming C applications to process networks in hardware
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
Sven van Haastregt, Bart Kienhuis
SI3D
2012
ACM
13 years 5 months ago
Decoupled deferred shading for hardware rasterization
In this paper we present decoupled deferred shading: a rendering technique based on a new data structure called compact geometry buffer, which stores shading samples independently...
Gabor Liktor, Carsten Dachsbacher
ICPP
2009
IEEE
15 years 4 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
TC
2010
14 years 8 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
ISCA
2007
IEEE
94views Hardware» more  ISCA 2007»
14 years 9 months ago
Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits
In recent years, quantum computing (QC) research has moved from the realm of theoretical physics and mathematics into real implementations [9]. With many different potential hardw...
Eric Chi, Stephen A. Lyon, Margaret Martonosi