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ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
15 years 6 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DSN
2005
IEEE
15 years 3 months ago
ReStore: Symptom Based Soft Error Detection in Microprocessors
Device scaling and large scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing par...
Nicholas J. Wang, Sanjay J. Patel
HPCA
1998
IEEE
15 years 2 months ago
Address Translation Mechanisms In Network Interfaces
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent ope...
Ioannis Schoinas, Mark D. Hill
BMCBI
2008
115views more  BMCBI 2008»
14 years 10 months ago
BioGraphE: high-performance bionetwork analysis using the Biological Graph Environment
Background: Graphs and networks are common analysis representations for biological systems. Many traditional graph algorithms such as k-clique, k-coloring, and subgraph matching h...
George Chin Jr., Daniel G. Chavarría-Mirand...
SCP
2008
128views more  SCP 2008»
14 years 9 months ago
Mobile JikesRVM: A framework to support transparent Java thread migration
Today's complex applications must face the distribution of data and code among different network nodes. Computation in distributed contexts is demanding increasingly powerful...
Raffaele Quitadamo, Giacomo Cabri, Letizia Leonard...