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ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
15 years 4 months ago
A massively scaleable decoder architecture for low-density parity-check codes
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
Anand Selvarathinam, Gwan Choi, Krishna Narayanan,...
CLUSTER
2009
IEEE
15 years 5 months ago
MDCSim: A multi-tier data center simulation, platform
Abstract—Performance and power issues are becoming increasingly important in the design of large cluster based multitier data centers for supporting a multitude of services. Desi...
Seung-Hwan Lim, Bikash Sharma, Gunwoo Nam, Eun-Kyo...
PDIS
1994
IEEE
15 years 2 months ago
Achieving Transaction Scaleup on Unix
Constructing scalable high-performance applications on commodity hardware running the Unix operating system is a problem that must be addressed in several application domains. We ...
Marie-Anne Neimat, Donovan A. Schneider
ECSA
2010
Springer
14 years 11 months ago
A Model for Dynamic Reconfiguration in Service-Oriented Architectures
Abstract. The importance of modelling the dynamic architectural characteristics of software systems has long been recognised. However, the nature of the dynamic architectural chara...
José Luiz Fiadeiro, Antónia Lopes
FCCM
1999
IEEE
146views VLSI» more  FCCM 1999»
15 years 3 months ago
Sepia: Scalable 3D Compositing Using PCI Pamette
We have implemented an image combining architecture that allows distributed rendering of a partitioned data set at interactive rates. The architecture achieves real-time frame rat...
Laurent Moll, Mark Shand, Alan Heirich