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» A Self-Reconfigurable Gate Array Architecture
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ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
15 years 3 months ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
15 years 3 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 7 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ISPD
2003
ACM
92views Hardware» more  ISPD 2003»
15 years 2 months ago
An architectural exploration of via patterned gate arrays
Chetan Patel, Anthony Cozzie, Herman Schmit, Lawre...
ARCS
2008
Springer
14 years 11 months ago
A Novel Routing Architecture for Field-Programmable Gate-Arrays
Alexander Danilin, Martijn T. Bennebroek, Sergei S...