Sciweavers

132 search results - page 18 / 27
» A Self-Tuning Configurable Cache
Sort
View
IJNSEC
2008
164views more  IJNSEC 2008»
15 years 3 months ago
Secure Real-Time Streaming Protocol (RTSP) for Hierarchical Proxy Caching
Proxies are commonly used to cache objects, especially multimedia objects, so that clients can enjoy better quality-of-service (QoS) guarantees such as smaller startup latency and...
Yeung Siu Fung, John C. S. Lui, David K. Y. Yau
JSA
2000
116views more  JSA 2000»
15 years 3 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
ISCA
2012
IEEE
302views Hardware» more  ISCA 2012»
13 years 6 months ago
Scale-out processors
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, ...
108
Voted
FPL
2009
Springer
120views Hardware» more  FPL 2009»
15 years 8 months ago
Using 3D integration technology to realize multi-context FPGAs
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
RSP
2000
IEEE
111views Control Systems» more  RSP 2000»
15 years 8 months ago
Reconfigurable Instruction Set Processors: A Survey
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...
Francisco Barat, Rudy Lauwereins