The n-step delayed sharing information structure is investigated. This information structure comprises of K controllers that share their information with a delay of n time steps. ...
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
This paper focuses on the development of a cost-aware Bayesian sequential decision-making strategy for the search and classification of multiple unknown objects over a given domain...
Yue Wang, Islam I. Hussein, Donald R. Brown, Richa...
In this paper we explore two alternative approaches to system diagnosis. The first strategy is based on testability analysis performed by SATAN tool. The second approach performed ...
We investigate runtime strategies for data-intensive applications that involve generalized reductions on large, distributed datasets. Our set of strategies includes replicated fi...