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» A Sequential Reduction Strategy
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ICCAD
2003
IEEE
161views Hardware» more  ICCAD 2003»
15 years 6 months ago
A General S-Domain Hierarchical Network Reduction Algorithm
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
Sheldon X.-D. Tan
ICDE
1999
IEEE
113views Database» more  ICDE 1999»
15 years 11 months ago
Parallel Algorithms for Computing Temporal Aggregates
The ability to model the temporal dimension is essential to many applications. Furthermore, the rate of increase in database size and response time requirements has outpaced advan...
Jose Alvin G. Gendrano, Bruce C. Huang, Jim M. Rod...
DAC
2005
ACM
15 years 10 months ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu
IPPS
2007
IEEE
15 years 4 months ago
Leakage Energy Reduction in Value Predictors through Static Decay
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
Juan M. Cebrian, Juan L. Aragón, José...
DSN
2009
IEEE
15 years 1 months ago
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
Chengmo Yang, Alex Orailoglu