188 search results - page 7 / 38 » A Simulator for the Reconfigurable Mesh Architecture |
EH
1999
IEEE
15 years 1 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
MVA
1994
14 years 11 months ago
1994
In our work we improve the EPPI programming environment, which was made in the University of Castilla - la Mancha one year ago. EPPI is a tool for simulating parallel algorithms t...
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ERSA
2010
14 years 7 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
RSP
1999
IEEE
15 years 1 months ago
1999
IEEE
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are stil...
FPGA
2000
ACM
15 years 1 months ago
2000
ACM
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...