188 search results - page 9 / 38 » A Simulator for the Reconfigurable Mesh Architecture |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
: The MASC model is a multi-SIMD model that uses control parallelism to coordinate the interaction of data parallel threads. It supports a generalized associative style of parallel...
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EXPCS
2007
15 years 1 months ago
2007
Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretica...
DDECS
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
VLSID
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...