177 search results - page 5 / 36 » A Single-Path Chip-Multiprocessor System |
129
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HIPEAC
2010
Springer
16 years 17 days ago
2010
Springer
As CMOS feature sizes venture deep into the nanometer regime, wearout mechanisms including negative-bias temperature instability and timedependent dielectric breakdown can severely...
132
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
129
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IEEEPACT
2009
IEEE
15 years 10 months ago
2009
IEEE
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
164
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LCTRTS
2010
Springer
15 years 1 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
181
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HIPEAC
2011
Springer
14 years 3 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...