340 search results - page 11 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
CORR
2007
Springer
14 years 11 months ago
2007
Springer
: New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology’s scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristi...
VLSID
2005
IEEE
16 years 3 days ago
2005
IEEE
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
In this paper, we present the rst chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-speci ed input signal patterns, and thermal boundar...
VLSID
2005
IEEE
16 years 3 days ago
2005
IEEE
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
ESANN
2004
15 years 1 months ago
2004
: The architecture of a complete image segmentation system and the development of an embedded VLSI low-power integrated circuit are reported. A neuromorphic engineering approach is...