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MJ
2006
145views more  MJ 2006»
14 years 9 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
93
Voted
TC
2010
14 years 7 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
ASAP
2004
IEEE
185views Hardware» more  ASAP 2004»
15 years 1 months ago
Families of FPGA-Based Algorithms for Approximate String Matching
Dynamic programming for approximate string matching is a large family of different algorithms, which vary significantly in purpose, complexity, and hardware utilization. Many impl...
Tom Van Court, Martin C. Herbordt
FPL
2005
Springer
114views Hardware» more  FPL 2005»
15 years 2 months ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
ASAP
2003
IEEE
113views Hardware» more  ASAP 2003»
15 years 2 months ago
A VLSI Architecture for Advanced Video Coding Motion Estimation
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in area of variable block searching motion est...
Swee Yeow, John V. McCanny