60 search results - page 8 / 12 » A System for Synthesizing Optimized FPGA Hardware from MATLA... |
ERSA
2006
14 years 11 months ago
2006
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
GLOBECOM
2006
IEEE
15 years 3 months ago
2006
IEEE
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
SIPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
88
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EMSOFT
2006
Springer
15 years 1 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
104
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FPGA
2004
ACM
15 years 2 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...