499 search results - page 17 / 100 » A Three-Phase Algorithm for Computer Aided siRNA Design |
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
TVLSI
2010
14 years 4 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
DAC
2011
ACM
13 years 9 months ago
2011
ACM
Technology scaling allows the integration of billions of transistors on the same die but CAD tools struggle in keeping up with the increasing design complexity. Design productivit...
DAC
2009
ACM
15 years 4 months ago
2009
ACM
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...
DAC
2003
ACM
15 years 2 months ago
2003
ACM
Coverage estimation for model checking quantifies the completeness of a set of properties. We present an improved version of the algorithm of Hoskote et al. [7] that applies to a...