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» A Three-Phase Algorithm for Computer Aided siRNA Design
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DAC
2006
ACM
16 years 24 days ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
DAC
2006
ACM
16 years 24 days ago
Process variation aware OPC with variational lithography modeling
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional ...
Peng Yu, Sean X. Shi, David Z. Pan
SLIP
2009
ACM
15 years 6 months ago
From 3D circuit technologies and data structures to interconnect prediction
New technologies such as 3D integration are becoming a new force that is keeping Moore’s law in effect in today’s nano era. By adding a third dimension in current 2D circuits...
Robert Fischbach, Jens Lienig, Tilo Meister
SAC
2006
ACM
15 years 5 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
DAC
2009
ACM
16 years 25 days ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...