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» A Three-Phase Algorithm for Computer Aided siRNA Design
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DAC
2009
ACM
16 years 24 days ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
DAC
2008
ACM
16 years 24 days ago
Stochastic modeling of a thermally-managed multi-core system
Achieving high performance under a peak temperature limit is a first-order concern for VLSI designers. This paper presents a new model of a thermally-managed system, where a stoch...
Hwisung Jung, Peng Rong, Massoud Pedram
DAC
2007
ACM
16 years 24 days ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DAC
2003
ACM
16 years 23 days ago
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses
We present practical algorithms for the synthesis of crosstalk cancelling equalizing filters. We examine designs optimized for the traditional l2 metric and introduce an approach ...
Jihong Ren, Mark R. Greenstreet
DAC
2004
ACM
15 years 5 months ago
Optical proximity correction (OPC): friendly maze routing
As the technology migrates into the deep submicron manufacturing (DSM) era, the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoid...
Li-Da Huang, Martin D. F. Wong