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ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
13 years 3 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...
69
Voted
ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
15 years 6 months ago
Phase-tracking loop based on delta-sigma oversampling architecture
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and...
Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takas...
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
15 years 6 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
98
Voted
ICPP
2000
IEEE
15 years 5 months ago
Issues in Designing and Implementing a Scalable Virtual Interface Architecture
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
Shailabh Nagar, Anand Sivasubramaniam, Jorge Rodri...
52
Voted
ISCAS
1999
IEEE
78views Hardware» more  ISCAS 1999»
15 years 5 months ago
Cost-effective low-power architectures of video coding systems
A new low-power design technique, multirate, has been used along with other methods such as look-ahead, pipelining in designing the cost-effective low-power architectures of video...
Jie Chen, K. J. Ray Liu