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» A Visual Approach to Validating System Level Designs
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DAC
2006
ACM
16 years 4 months ago
Predicate learning and selective theory deduction for a difference logic solver
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
Chao Wang, Aarti Gupta, Malay K. Ganai
131
Voted
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
15 years 9 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
MM
2004
ACM
192views Multimedia» more  MM 2004»
15 years 9 months ago
Communicating everyday experiences
In this paper, we present our approach to the problem of communicating everyday experiences. This is a challenging problem, since media from everyday events are unstructured, and ...
Preetha Appan, Hari Sundaram, David Birchfield
131
Voted
DAC
2001
ACM
16 years 4 months ago
Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
William J. Dally, Brian Towles
127
Voted
ASE
2008
102views more  ASE 2008»
15 years 3 months ago
Model driven code checking
Model checkers were originally developed to support the formal verification of high-level design models of distributed system designs. Over the years, they have become unmatched in...
Gerard J. Holzmann, Rajeev Joshi, Alex Groce