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» A comparative study of power efficient SRAM designs
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GLVLSI
2000
IEEE
82views VLSI» more  GLVLSI 2000»
15 years 2 months ago
A comparative study of power efficient SRAM designs
Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane...
ETS
2010
IEEE
153views Hardware» more  ETS 2010»
14 years 8 months ago
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
ÑIn this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analy...
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio,...
ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
14 years 10 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
ISQED
2008
IEEE
120views Hardware» more  ISQED 2008»
15 years 4 months ago
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja...
ICCAD
2010
IEEE
133views Hardware» more  ICCAD 2010»
14 years 7 months ago
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia...