Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
PDF Tools
Image Tools
Text Tools
OCR Tools
Symbol and Emoji Tools
On-screen Keyboard
Latex Math Equation to Image
Smart IPA Phonetic Keyboard
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
Free Online Productivity Tools
i2Speak
i2Symbol
i2OCR
iTex2Img
iWeb2Print
iWeb2Shot
i2Type
iPdf2Split
iPdf2Merge
i2Bopomofo
i2Arabic
i2Style
i2Image
i2PDF
iLatex2Rtf
Sci2ools
72
Voted
GLVLSI
2000
IEEE
82
views
VLSI
»
more
GLVLSI 2000
»
A comparative study of power efficient SRAM designs
15 years 7 months ago
Download
www.cecs.uci.edu
Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane
Real-time Traffic
GLVLSI 2000
|
VLSI
|
claim paper
Related Content
»
Analysis of resistivebridging defects in SRAM corecells A comparative study from 90nm down...
»
An energy efficient cache design using spin torque transfer STT RAM
»
ErrorTolerant SRAM Design for UltraLow Power Standby Operation
»
Testing methods for detecting stuckopen power switches in coarsegrain MTCMOS designs
»
Pareto Points in SRAM Design Using the Sleepy Stack Approach
»
A Combined DOEILP Based Power and Read Stability Optimization in NanoCMOS SRAM
»
Low power 8T SRAM using 32nm independent gate FinFET technology
»
Design of an H264AVC Decoder with Memory Hierarchy and LinePixelLookahead
»
A low leakage 9t sram cell for ultralow power operation
more »
Post Info
More Details (n/a)
Added
31 Jul 2010
Updated
31 Jul 2010
Type
Conference
Year
2000
Where
GLVLSI
Authors
Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin
Comments
(0)
Researcher Info
VLSI Study Group
Computer Vision