39 search results - page 1 / 8 » A frequency synthesizer using two different delay feedbacks |
ISCAS
2005
IEEE
13 years 12 months ago
2005
IEEE
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
Several approaches to post-silicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit a...
ISCAS
2006
IEEE
14 years 9 days ago
2006
IEEE
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
ISCAS
2006
IEEE
14 years 9 days ago
2006
IEEE
—We present an efficient approach for on-chip frequency response measurement, including phase and gain, of analog circuitry in mixed-signal systems. The approach uses direct digi...
GLOBECOM
2006
IEEE
14 years 10 days ago
2006
IEEE
— In this paper, we consider beamforming with finite– rate feedback for frequency–selective channels with decisionfeedback equalization (DFE) at the receiver. Using average ...