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IJNSEC
2008
106views more  IJNSEC 2008»
15 years 1 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
CAINE
2006
15 years 3 months ago
A novel parallel hardware and software solution for a large-scale biologically realistic cortical simulation
This research addresses a major gap in our conceptual understanding of synaptic and brain-like network dynamics. Over the course of several years we have designed and implemented ...
Frederick C. Harris Jr., Mark C. Ballew, Jason Bau...
IPPS
2010
IEEE
14 years 11 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
15 years 8 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
IPPS
2007
IEEE
15 years 8 months ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel