326 search results - page 11 / 66 » A hierarchical modeling framework for on-chip communication ... |
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
Interprocessor communication times can be a significant fraction of the overall execution time required for data parallel applications. Large communication to computation ratios o...
NIPS
2004
14 years 11 months ago
2004
We study the synthesis of neural coding, selective attention and perceptual decision making. We build a hierarchical neural architecture that implements Bayesian integration of no...
PEWASUN
2005
ACM
15 years 3 months ago
2005
ACM
Scalability issues for routing in mobile ad hoc networks (MANETs) have been typically addressed using hybrid routing schemes operating in a hierarchical network architecture. Seve...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...