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» A low power architecture for embedded perception
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ESORICS
2009
Springer
15 years 10 months ago
Cumulative Attestation Kernels for Embedded Systems
1 There are increasing deployments of networked embedded systems and rising threats of malware intrusions on such systems. To mitigate this threat, it is desirable to enable common...
Michael LeMay, Carl A. Gunter
TCSV
2002
103views more  TCSV 2002»
14 years 9 months ago
A scalable and programmable architecture for 2-D DWT decoding
The compression of still images by means of the discrete wavelet transform (DWT), adopted in the JPEG-2000 and MPEG-4 standards, is becoming more and more widespread because it yie...
Massimo Ravasi, L. Tenze, Marco Mattavelli
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 1 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
MAM
2002
110views more  MAM 2002»
14 years 9 months ago
Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeline...
Ernesto Martins, Paulo A. C. S. Neves, José...
DAC
2007
ACM
15 years 10 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid