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» A low power high performance switched-current multiplier
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ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
15 years 6 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
101
Voted
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
15 years 5 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram
WWIC
2005
Springer
137views Communications» more  WWIC 2005»
15 years 7 months ago
Providing Delay Guarantees and Power Saving in IEEE 802.11e Network
Recently, the 802.11e Working Group (WG) has proposed the Hybrid Coordination Function (HCF), which has a HCF Controlled Channel Access (HCCA) and an Enhanced Distributed Coordinat...
Gennaro Boggia, Pietro Camarda, F. A. Favia, Luigi...
90
Voted
IBMRD
2006
63views more  IBMRD 2006»
15 years 1 months ago
Decomposing the load-store queue by function for power reduction and scalability
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
Lee Baugh, Craig B. Zilles
ICC
2008
IEEE
133views Communications» more  ICC 2008»
15 years 8 months ago
Memoryless Relay Strategies for Two-Way Relay Channels: Performance Analysis and Optimization
— We consider relaying strategies for two-way relay channels, where two terminals transmits simultaneously to each other with the help of relays. A memoryless system is considere...
Tao Cui, Jörg Kliewer