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» A methodology for generating verified combinatorial circuits
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ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
14 years 3 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
14 years 9 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
ISLPED
2010
ACM
236views Hardware» more  ISLPED 2010»
14 years 11 months ago
Analysis and design of ultra low power thermoelectric energy harvesting systems
Thermal energy harvesting using micro-scale thermoelectric generators is a promising approach to alleviate the power supply challenge in ultra low power systems. In thermal energy...
Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaush...