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ICCD
2007
IEEE
183views Hardware» more  ICCD 2007»
15 years 6 months ago
Constraint satisfaction in incremental placement with application to performance optimization under power constraints
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
Huan Ren, Shantanu Dutt
CLEIEJ
2010
14 years 7 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
BMCBI
2010
143views more  BMCBI 2010»
14 years 9 months ago
An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location inf
Background: Graph drawing is one of the important techniques for understanding biological regulations in a cell or among cells at the pathway level. Among many available layout al...
Kaname Kojima, Masao Nagasaki, Satoru Miyano
FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
15 years 1 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
DATE
2005
IEEE
101views Hardware» more  DATE 2005»
15 years 3 months ago
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
Christophe Alexandre, Hugo Clément, Jean-Pa...