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» A new decentralization technique for interconnected systems
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 4 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
HPDC
2007
IEEE
15 years 6 months ago
Using content-addressable networks for load balancing in desktop grids
Desktop grids combine Peer-to-Peer and Grid computing techniques to improve the robustness, reliability and scalability of job execution infrastructures. However, efficiently mat...
Jik-Soo Kim, Peter J. Keleher, Michael A. Marsh, B...
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
15 years 5 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
15 years 8 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
132
Voted
BMCBI
2005
156views more  BMCBI 2005»
14 years 11 months ago
A new dynamical layout algorithm for complex biochemical reaction networks
Background: To study complex biochemical reaction networks in living cells researchers more and more rely on databases and computational methods. In order to facilitate computatio...
Katja Wegner, Ursula Kummer