1017 search results - page 63 / 204 » A routing algorithm for flip-chip design |
132
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GLVLSI
2007
IEEE
15 years 7 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
103
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ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
122
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MOBICOM
2003
ACM
15 years 6 months ago
2003
ACM
We develop algorithms for finding minimum energy disjoint paths in an all-wireless network, for both the node and linkdisjoint cases. Our major results include a novel polynomial...
105
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FOCS
2006
IEEE
15 years 7 months ago
2006
IEEE
In this work we study a wide range of online and offline routing and packing problems with various objectives. We provide a unified approach, based on a clean primal-dual method...
DFT
1997
IEEE
15 years 5 months ago
1997
IEEE
Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits...