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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 4 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
113
Voted
IJNS
2000
130views more  IJNS 2000»
14 years 9 months ago
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
Teresa Serrano-Gotarredona, Andreas G. Andreou, Be...
EUROPLOP
2006
14 years 11 months ago
Patterns for Adaptive Service-Centric Systems
Service-centric systems are driven more and more towards self-adaptation in order to satisfy QoS in highly dynamic environments. However, the young age and immaturity of this doma...
Paris Avgeriou
102
Voted
HPCA
2006
IEEE
15 years 10 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
12 years 12 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...