80 search results - page 2 / 16 » ALBORZ: Address Level Bus Power Optimization |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
106
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CDC
2010
IEEE
14 years 4 months ago
2010
IEEE
This paper is concerned with studying how the minimum power loss in a power system is related to its network topology. The existing algorithms in the literature all exploit nonline...
111
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
ASPLOS
2004
ACM
15 years 2 months ago
2004
ACM
+ XOM-based secure processor has recently been introduced as a mechanism to provide copy and tamper resistant execution. XOM provides support for encryption/decryption and integrit...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...