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ICSE
2003
IEEE-ACM
16 years 16 days ago
Improving Test Suites via Operational Abstraction
g Test Suites via Operational Abstraction Michael Harder Jeff Mellen Michael D. Ernst MIT Lab for Computer Science 200 Technology Square Cambridge, MA 02139 USA {mharder,jeffm,mern...
Michael Harder, Jeff Mellen, Michael D. Ernst
102
Voted
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 4 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
TVLSI
2008
140views more  TVLSI 2008»
15 years 10 days ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
92
Voted
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 7 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
95
Voted
DAC
2003
ACM
16 years 1 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv