Sciweavers

214 search results - page 7 / 43
» Abstraction and extensibility in digital logic simulation so...
Sort
View
CN
2000
128views more  CN 2000»
14 years 9 months ago
The Network Workbench: network simulation software for academic investigation of Internet concepts
Simulation offers significant advantages as a basis for academic projects in computer networking. many unimportant details can be abstracted away, and also because simulations can...
J. Mark Pullen
SPIN
2004
Springer
15 years 3 months ago
Model-Driven Software Verification
Abstract. In the classic approach to logic model checking, software verification requires a manually constructed artifact (the model) to be written in the language that is accepted...
Gerard J. Holzmann, Rajeev Joshi
FORMATS
2010
Springer
14 years 7 months ago
Simulation and Bisimulation for Probabilistic Timed Automata
Abstract. Probabilistic timed automata are an extension of timed automata with discrete probability distributions. Simulation and bisimulation relations are widely-studied in the c...
Jeremy Sproston, Angelo Troina
PADS
2003
ACM
15 years 3 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
EMSOFT
2005
Springer
15 years 3 months ago
Communication strategies for shared-bus embedded multiprocessors
Abstract— This paper explores the problem of efficiently ordering interprocessor communication operations in both statically and dynamically-scheduled multiprocessors for iterat...
Neal K. Bambha, Shuvra S. Bhattacharyya