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PCI
2005
Springer
15 years 3 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
ASSETS
2004
ACM
15 years 3 months ago
Middleware to expand context and preview in hypertext
Movement, or mobility, is key to the accessibility, design, and usability of many hypermedia resources (websites); and key to good mobility is context and preview by probing. This...
Simon Harper, Carole A. Goble, Robert Stevens, Yel...
JELIA
2004
Springer
15 years 3 months ago
Logic Programming Infrastructure for Inferences on FrameNet
Abstract. The growing size of electronically available text corpora like companies’ intranets or the WWW has made information access a hot topic within computational linguistics....
Peter Baumgartner, Aljoscha Burchardt
ICASSP
2010
IEEE
14 years 8 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Althou...
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija...
CONEXT
2009
ACM
14 years 11 months ago
Cool-Tether: energy efficient on-the-fly wifi hot-spots using mobile phones
We consider the problem of providing ubiquitous yet affordable Internet connectivity to devices at home, at work, and on the move. In this context, we take advantage of two signif...
Ashish Sharma, Vishnu Navda, Ramachandran Ramjee, ...