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ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 5 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
SLIP
2009
ACM
15 years 6 months ago
A pre-placement net length estimation technique for mixed-size circuits
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
Bahareh Fathi, Laleh Behjat, Logan M. Rakai
TECS
2008
122views more  TECS 2008»
14 years 11 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
ICASSP
2011
IEEE
14 years 3 months ago
Stochastic behavior analysis of the Gaussian Kernel Least Mean Square algorithm
Like its linear counterpart, the Kernel Least Mean Square (KLMS) algorithm is also becoming popular in nonlinear adaptive filtering due to its simplicity and robustness. The “k...
Wemerson D. Parreira, José Carlos M. Bermud...
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
15 years 6 months ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li