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» Accurate and scalable reliability analysis of logic circuits
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CODES
2010
IEEE
14 years 9 months ago
A task remapping technique for reliable multi-core embedded systems
With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software so...
Chanhee Lee, Hokeun Kim, Hae-woo Park, Sungchan Ki...
ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
14 years 3 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
HOTOS
2009
IEEE
15 years 3 months ago
FLUXO: A Simple Service Compiler
In this paper, we propose FLUXO, a system that separates an Internet service's logical functionality from the architectural decisions made to support performance, scalability...
Emre Kiciman, V. Benjamin Livshits, Madanlal Musuv...
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
15 years 3 months ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
15 years 4 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...