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ICMCS
2005
IEEE
109views Multimedia» more  ICMCS 2005»
15 years 7 months ago
H.264 HDTV Decoder Using Application-Specific Networks-On-Chip
This paper studied an H.264 HDTV decoder on two multiprocessor system-on-chip architectures. Two types of networks-on-chip, the RAW network and the applicationspecific networks-on...
Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. ...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 6 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 6 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
SCALESPACE
2001
Springer
15 years 6 months ago
Down-Scaling for Better Transform Compression
Abstract. The most popular lossy image compression method used on the Internet is the JPEG standard. JPEG’s good compression performance and low computational and memory complexi...
Alfred M. Bruckstein, Michael Elad, Ron Kimmel
MASCOTS
2003
15 years 2 months ago
An Evaluation Framework For Active Queue Management Schemes
Over the last decade numerous Active Queue Management (AQM) schemes have been proposed in the literature. Many of these studies have been directed towards improving congestion con...
Arkaitz Bitorika, Mathieu Robin, Meriel Huggard